Our Client, a leader in the industry, is looking for a Design Verification Engineer in its San Diego location for a long-term contract position. The successful candidate will primarily support and manage the test and design verification.
Define testbench infrastructure using System Verilog, UVM and Formal
Assist in complete verification of high performance, high speed, low power ASIC
Guide the development of comprehensive, flexible, and portable block to chip level testbench, detailed test plans and coverage closure
Infrastructure work including developing scripts, methodologies and tools for efficiency and quality improvements
Education Requirements MS/EE or CS
3 Years relevant work experience
Strong verification skills including a good knowledge and understanding of different verification methodologies
Past experience of successfully technically guiding complex, high speed design verification
Strong skills in testbench creation, debugging failures, and coverage closure
Self-motivated, good communicator, quick learner and good team player
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